1. Field of the Invention
The present invention relates to the field of use of image capturing using complementary metal-oxide semiconductor (CMOS) sensors. More particularly, the present invention relates to providing exposure control for CMOS sensors.
2. Description of Related Art
A video frame is composed of an array of pixels (picture elements) composed of CMOS sensor cells arranged in a grid of columns and rows—i.e. an array of CMOS sensor cells. Each cell in the array of CMOS sensor cells responds to light by storing a proportional amount of charge. The more light a CMOS sensor cell is exposed to, the more charge that CMOS sensor cell stores. For a monochrome (i.e., gray-scale) picture, the intensity of each pixel can be calculated by determining the amount of charge stored by the respective CMOS sensor cell, with a higher amount of charge representing that the CMOS sensor cell being exposed to more light. Similarly, for a color video frame, each pixel is represented by a block of three or more adjacently located CMOS sensor cells, where each CMOS sensor cell captures the intensity of one of the three colors: red, green, and blue.
For example, in a CMOS sensor cell array 2 shown in FIG. 1, each cell represents one pixel in a monochrome picture. The picture is formed by measuring the charges stored in each CMOS sensor cell, a row at a time. For example, a CMOS sensor cell [0,0], a CMOS sensor cell [0,1] and the other CMOS sensor cells of row 0 (not shown) simultaneously place their charges on a data signal line D0, a data signal line D1, and the other data signal lines of CMOS sensor cell array 2 (not shown), respectively, when a read signal is applied to row 0 signal line. Moreover, CMOS sensor cell [0,0], CMOS sensor cell [0,1] and the other CMOS sensor cells of row 0 are simultaneously drained of their charges when a reset signal is applied to reset 0 signal line. Thus, the charge in CMOS sensor cell [0,0] is output when a read signal is applied to row 0 signal line and the charge in CMOS sensor cell [0,0] is reset (i.e., cleared) when a reset signal is applied to reset 0 signal line.
Each row signal line and each reset signal line is reached through an AND gate (i.e., each row signal line and each reset signal line is connected to the output of an AND gate). The two AND gates for each row share a common input such that the row signal line and reset signal line for each row are addressable by a single address signal line. For example, row 0 signal line and reset 0 signal line are accessible only when addr 0 signal line receives an address signal with a logical value of “1”, allowing AND gate 8 and AND gate 10 to allow the signals on rowgen signal line 12 and rstgen signal line 14, respectively, to be passed through to row 0 signal line and reset 0 signal line, respectively. Conversely, no row can be reset or read unless the associated address signal line has a logical value of “1” as otherwise the AND gates for the row will not allow any signals to pass.
FIG. 1, a “post-capture” circuit utilizing analogto-digital (A/D) converters and digital latches is used to generate each frame of the image as follows. First, the amount of charge contained in each CMOS sensor cell is “digitized” to obtain a quantified amount by A/D converters. The output of each A/D converter is fed into the first digital latch of a series of digital latches, the set of values shifting over as every row is captured.
The measurement of the charge for each of the cells is. converted from an analog level to a digital level through the use of a single analog-to-digital converter for each column. Thus, A/D 16 is responsible for converting the level of charge contained in CMOS sensor cell [0,0] after the charge has been placed on data signal line D0, as described above, from an analog signal to a digital value. This digital value is stored in a digital latch 18. As there are four rows in CMOS sensor cell array 2 (i.e. four CMOS sensor cells in each column), four digital latches per column are used to store the measured values of the set of cells in each column.
FIG. 2 is a timing/signal diagram showing the operation of the circuit of FIG. 1. rowgen signal line 12 and rstgen signal line 14 receives regular clock pulses, while access 0 signal line, access 1 signal line, access 2 signal line, and access 3 signal line are “strobed” cyclically. The values appearing on the row signal lines of each row is the logical AND of the values on rowgen signal line 12 and the respective address signal line (i.e., access 0 signal line, access 1 signal line, acces 2 signal line, and access 3 signal line). Similarly, the values appearing on the reset signal lines of each row is the logical AND of the values on rstgen signal line 14 and the respective address signal line.
For example, referring to FIG. 2, at time t1, access 0 signal line undergoes a low to high signal transition after which rowgen signal line 12 also undergoes a low to high signal transition. The resulting AND operation performed by AND gate 8 produces a logical “1” at row signal line 4, which causes the CMOS sensor cells of row 0 to output their charges onto the data signal lines to be converted by the associated A/D converters.
After rowgen signal line 12 undergoes a high to low signal transition, rstgen signal line 14 undergoes a low to high signal transition. The resulting AND operation performed by AND gate 10 produces a logical “1” at reset 0 signal line, which causes the CMOS sensor cells for row 0 to be drained of their charges and, thus, be ready to accumulate charge again.
At time t2, at the transition of rstgen signal line 14 from a high to low signal, CMOS sensor cell [0,0] has been completely discharged. Thereafter, access 0 signal line undergoes a high to low signal transition, which will prevent any value transitions on rowgen signal line 12 and rstgen signal line 14 from affecting row 0 signal line and reset 0 signal line, respectively, until time t3, as described below.
From the high to low signal transition of access 0 signal line immediately after time t2 to time t3, the other address signal lines (i.e., access 1 signal line, access 2 signal line, and access 3 signal line) also undergo the same transitions in sequence, which affects the row signal line and the reset signal line of each corresponding row in the manner described above.
At time t3, when access 0 signal line undergoes a low to high signal transition again, the CMOS sensor cells for row 0 has accumulated charge from time t2 to time t3. The CMOS sensor cells for row 0 accumulate charge until time. t4, when the charge for each CMOS sensor cell is read out as described above. Thus, the total charge accumulation time is from time t2 (when the CMOS sensor cells of row 0 are reset) to time t4 (when the CMOS sensor cells of row 0 are read). This charge accumulation time is equal for every cell in every row as the transitions for rowgen signal line 12, rstgen signal line 14, access 0 signal line, access 1 signal line, access 2 signal line and access 3 signal line have the same respective frequency and only differ as to their periods.
The amount of charge stored by each CMOS sensor cell is proportional to the amount of time the CMOS sensor cell is exposed to light. As the amount of charge each CMOS sensor cell is capable of storing is limited, the amount of time each CMOS sensor cell is exposed to light is limited at the upper end by the amount of storable charge (i.e. charge accumulation time is limited in a practical sense by the amount of storable charge). In order for CMOS sensor cell array 2 to be able to operate under a variety of lighting conditions, the amount of time for which CMOS sensor cell array 2 is exposed to light has to be controlled. Otherwise, in highly lit situations such as the outdoors during a sunny day, all the CMOS sensor cells would be saturated, returning a white picture. Similarly, in lowly lit situations such as during evening periods, all of the CMOS sensor cells would return very little charge, resulting in a substantially black picture.
To compensate for the former situation, the CMOS sensor cells can be made less sensitive to light (i.e., the CMOS sensor cells stores charge slowly under all conditions). However, this would exacerbate the problem of the CMOS sensor cells not being “sensitive” enough under low-light conditions. Thus, preferably, the CMOS sensor cells are manufactured to be sensitive to low-light situations and, for highly lit situations, are “protected” from too much exposure to light through the use of an iris.
Normally, the iris can grossly adjust the amount of light that is allowed to reach CMOS sensor cell array 2. Thus, the iris can control the amount of light reaching CMOS sensor cell array 2 in any charge accumulation period. However, under many circumstances, this amount of adjustment is not accurate enough, therefore still resulting in either over-exposure or under-exposure of the CMOS sensor cells. For example, in video capturing applications (when frame rates are currently targeted at approximately 30 frames per second), the targeted range of exposure time for CMOS sensor cell array 2 is from a minimum time of {fraction (1/30)}th of a second and lower, (i.e., 30 Hz and up). At these rates, it would not be sufficient to just use the gross adjustment provided by an iris.
Therefore, to compensate for any adjustments necessary due to the inadequacy of the iris, the post-capture circuitry is set to operate at a rate high enough to effectively allow each frame to be captured (i.e., each row to be processed) before the CMOS sensor cells become saturated due to over-exposure.
However, with current CMOS sensor cell technology, the amount of time required to capture and process a row (i.e., the amount of time required for the charge contained in each CMOS sensor cell to be measured by an A/D converter) is fixed and relatively large in comparison to the desired minimum exposure time. Thus, there is a limit to the speed of operation of the post-capture circuitry.
One solution that has been proposed is to increase the speed of operation of the post-capture circuitry to capture each row at the desired speed. However, assuming what is desired is a capture resolution at 1,000 rows of 1,000 CMOS sensor cells per row (i.e., 1,000×1,000 resolution), there would need to be 1,000 rows that would need to be processed every {fraction (1/30)}th of a second on the low end, 1/xth of a second on the high end (where x can be any number required to capture the image, and can be on the order of hundreds, and thousands, even higher numbers). Although CMOS sensor cells can be made sensitive enough to capture at the required rates, to increase the speed of the post-capture circuitry to be able to process the incoming data at the required rate would be prohibitively expensive.
In addition, this increased speed is unnecessary as the required frame rate is only 30 frames per second. Thus, any operation rate higher than 30 Hz (i.e. {fraction (1/30)}th of a second) would be unnecessary for most products in question.
What is required, therefore, is a uniform control for a wide range of exposure times on a per row basis given a fixed frame capture time. This means that for a given frame rate, the exposure time for the CMOS sensor array can be any arbitrary period such that, if the situation requires, the frame rate can remain constant while only the exposure time of each frame is varied (i.e., even though a frame needs to be captured every {fraction (1/30)}th of a second), the exposure time would be controllable to be a period shorter than the {fraction (1/30)}th of a second period.